(a) Field of the Invention
The present invention relates to a semiconductor device and, more particularly, to an improvement in contact structure connecting an active region to a wiring layer or in a through-hole structure for interconnecting a lower and an upper wiring layers.
(b) Description of the Related Art
Recently, a contact electrode or through-hole in a semiconductor device has been made smaller in a cross sectional view for increasing the integration density of the semiconductor device. Conductive layers for interconnection wiring patterns to be electrically connected to the contact electrodes have also been made smaller in line width and in a gap between adjacent lines.
Accordingly, it is a critical factor in the miniaturization of a semiconductor device to obtain a sufficient contact area for connecting the contact electrode or through-hole with the overlying interconnection wiring layer.
It is also an extremely important factor in the miniaturization of a semiconductor device to reduce a margin area while assuring an alignment between the contact electrode or through-hole and the overlying interconnection wiring layer, even when an avoidable misregistration or size variation occurs during the fabrication process.
In short, miniaturization of the semiconductor device is restricted to a certain degree by the necessary contact area between the contact electrode or through-hole and the overlying interconnection wiring layer and by the necessary margin area for an alignment between the contact electrode and the overlying interconnection wiring layer.